8051 IP Cores
... memory mapped peripherals
T8032: Wishbone bus interface
Features
All peripherals/interrupts implemented
Single cycle per byte fetch
Supports synchronous RAM/ROM
Single cycle MOVX (8052) ...
8051 Instruction Set
...
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
E0
MOVX
AJMP
...
8051 Opcodes
...
DB
2
DJNZ
R3, offset
DC
2
DJNZ
R4, offset
DD
2
DJNZ
R5, offset
DE
2
DJNZ
R6, offset
DF
2
DJNZ
R7, offset
E0
1
MOVX
A, @DPTR
E1 ...